The present invention relates to the use of thin film deposition technology to create high density interconnects on a printed wiring board substrate. More specifically, the present invention pertains to an improved method for controlling the impedance of signal lines formed on a high-density interconnect substrate. The present invention increases the surface area available for routing wiring having improved impedance characteristics. The method of the present invention can be used with or without an initial build-up layer on a printed wiring substrate provided by a substrate vendor, and is useful for high density integrated circuit packaging of single chip or multi-chip hybrid circuits including components such as resistors and capacitors. The method of the present invention is also useful for creating interconnections on high-density xe2x80x9cdaughterxe2x80x9d boards that carry packaged devices.
The semiconductor industry continues to produce integrated circuits of increasing complexity and increasing density. The increased complexity of some of these integrated circuits has in turn resulted in an increased number of input/output pads on the circuit chips. At the same time, the increased density of the chips has driven the input/output pad pitch, i.e. the spacing between pads, downward. The combination of these two trends has been both a significant increase in the connector pin wiring density and closer spacing of the pins. Concurrent with this increased pin density and lower pitch has been an increase in the frequency of signals that are sent through the wiring substrate. A simple, uncharacterized wire is no longer optimum for these high frequency signals, and a signal line having a selected characteristic is desired. In other words, it is desirable that the signal lines are transmission lines with a known and controlled characteristic impedance.
A number of different technologies have been developed to interconnect multiple integrated circuits and related components. One such technology, based on traditional printed wiring board (xe2x80x9cPWBxe2x80x9d) technology is often referred to as MCM-L or laminate MCM technology. This technology found wide use during the period in which integrated circuits were packaged in dual-in-line packages (xe2x80x9cDIPsxe2x80x9d). MCM-L technology typically uses sub-laminate boards of copper foil and dielectric material layers to create a laminated interconnect structures. Conductive patterns on the sub-laminate in MCM-L process are typically formed using a dry film of photo resist over the copper layer, patterning and developing the photo resist to from an appropriate mask, and selectively etching away the unwanted copper, thereby leaving the desired patterned conductive layer.
Substrates used in MCM-L technology can be manufactured in large-area panels that are efficient and relatively low-cost. Interconnect solutions using this technology generally have relatively good performance characteristics when used with the generally wide-pitch, low pin density DIP components. The printed wiring board industry, however, has not kept pace with the advances in semiconductor manufacturing in terms of pad density.
In some applications, two or more sub-laminates are stacked together to form a final, stacked structure, or multi-layer laminated printed wiring substrate. Interconnection between stacked layers can be provided by a plated through hole (xe2x80x9cPTHxe2x80x9d). One way to make a PTH is to drill a hole through the board, and then plate the interior surface of the hole. The drilling process is relatively slow and expensive and can require a large amount of board space, thus reducing the area available for signal routing. As the number of interconnect pads increases, an increased number of signal layers is often used to form the interconnect structure. Because of these limitations, the conventional printed wiring board technology needs to use a large number of metal layers (e.g. greater than eight layers for some of the applications) in high density integrated circuit packaging and daughter board fabrication. Utilizing a large number of metal layers in this context generally increases cost and decreases electrical performance. Also, the pad size limits the wiring density on any given layer with this technology. Thus, MCM-L technology, while useful for some applications, is not capable of providing the connection density required in other applications.
To improve the interconnect density of MCM-L technology, an advanced printed wiring board technology approach called build-up multi-layer has been developed. In this technology a traditional laminated printed wiring board core is the starting point. Standard drilling and plating techniques are used to form plated through holes in the core. From the basic core this build-up approach has many variations. Typically, a dielectric layer approximately 50 micrometers thick is formed on the top, bottom, or both major surfaces of the laminated wiring board substrate, although in some instances the layer may be only about 30 microns thick. Vias are formed in the build-up layer by laser ablation, photo mask/plasma etch, photo exposure and development, or other methods. An electroless seeding step is then done prior to a panel plating step to metallize the surface(s) of the dielectric layer(s). The metal layer is typically 10-15 microns thick, but could be as thin as 4-5 microns. Typically, subsequent masking and wet etching steps then define a desired conductive pattern in the metal layer on the build-up dielectric layer.
Another approach used to package high density input/output uses thick film (i.e. screen printing) over co-fired ceramic substrates. This technology is sometimes referred to as xe2x80x9cMCM-Cxe2x80x9d, for co-fired ceramic MCM and thick film MCM technology. Basically, MCM-C technology involves rolling a ceramic mixture into sheets, drying the sheets, punching vias through the green ceramic sheets, screening the rolled sheets with a metal paste to form an electrical trace pattern on the surface of the ceramic sheet(s), stacking and laminating all the sheets together, then co-firing at a high temperature (e.g. typically at a temperature greater than 850xc2x0 C.) to form a substrate assembly with the desired interconnections.
MCM-C construction has found extensive use in high density and high reliability products where the robustness of the high density interconnect package outweighs the cost considerations. The ability to create a hermetic seal in the ceramic improves the ability to withstand environments not tolerable to conventional printed wiring board technology. While this technology is capable of high-density packaging applications (e.g. greater than 1000 pads), it is also very costly. Additionally, performance characteristics, such as signal propagation time, are affected by the relatively high dielectric constant (e.g. typically between 5.0 and 9.0) of the ceramic material. MCM-C technology provides higher connection density than MCM-L technology, but is not capable of providing the connection density required for some of today""s high density interconnect applications, and is difficult to use to produce large panels.
A third approach which the high density interconnect and packaging industry has moved toward to address these high density interconnect applications uses thin film MCM technology and is sometimes referred to as xe2x80x9cMCM-Dxe2x80x9d for MCM deposition technology. In some applications, such MCM-D technology includes forming and patterning thin film conductive traces over large substrates such as the laminated printed wiring boards discussed above. Such large substrates may have a surface area of 40 centimeters by 40 centimeters or more, thereby providing efficiencies that lower the costs of production. This type of technology is also sometimes referred to as xe2x80x9cDONLxe2x80x9d for deposited-on-laminate.
MCM-D technology utilizes a combination of low cost printed wiring board structures, with or without the use of the build-up multi-layers (i.e. a build-up layer and a first metal layer supplied by the substrate vendor) on the laminated printed wiring board, as a starting point to meet higher density and lower cost interconnect requirements. One feature of MCM-D technology is that it can produce a high-density interconnect substrate using thin film processes on only one side of the printed wiring board. The total thickness of several of these deposited layers can be less than the thickness of a single traditional build-up layer. This can eliminate the need for balancing the build-up layers on both top and bottom to prevent the substrate from warping.
Despite the definite advantages of MCM-D technology, there are potential problems that may result in failure modes and performance limitations if the thin film formation is not properly implemented. One such limitation resulting from improperly deposited thin film build-up layers is sub-optimized inter-layer impedance. The thin-film techniques used in MCM-D technology can provide for narrow, closely spaced signal lines in the patterned conductor layer, and for a conductor layer that is separated from another conductor layer by a relatively very thin dielectric layer. These and other factors can result in a signal line of high and/or varying impedance.
Accordingly, improved methods and structures are desirable to control the impedance of signal lines in the build-up portion of MCM-D substrates.
The present invention provides a solution to the problem of controlling the impedance of signal lines in the build-up layers of printed circuit wiring substrates. The invention enables a higher portion of the total number of signal lines to achieve a desired impedance, and to reduce the uncontrolled impedance effects on the electrical performance of the high density interconnect device. Alternatively or additionally, the invention enables greater freedom in choosing a routing pattern for signal lines while retaining a desired impedance. The present invention provides a significant increase in ground reference plane area, providing increased routing of signal lines over a reference plane to achieve a controlled characteristic impedance. In one embodiment, increased pad density and a transition between a coarse pad pitch, e.g. 1 mm, and a fine pad pitch, e.g. less than or equal to about 0.1 mm, is also achieved.
According to one embodiment of the present invention, a planarized layer is formed on a laminated printed wiring substrate to improve the electrical performance of the layer and allow for finer geometry processes to define a subsequent metal layer. In one embodiment this metal layer is a thin-film layer formed by sputtering, also known as physical vapor deposition (xe2x80x9cPVDxe2x80x9d), or pattern plating. The fine-geometry achieved by the combination of the planarized layer and subsequent thin-film metal layer results in a smaller pad footprint, allowing more of the metal layer to serve as a xe2x80x9cgroundxe2x80x9d (reference) plane. Alternatively, the fine-geometry methods allow definition of narrower signal lines, allowing more signal lines to be routed in a selected area, and/or allowing greater flexibility in the placement of signal lines. The use of thin layers also preserves the planarity of the surface of the thin film stack as it is built on the substrate, especially in conjunction with liquid dielectric layer precursors.
In a further embodiment, a thin dielectric layer is formed over the first thin-film metal layer and a second thin-film metal layer is formed over the thin dielectric layer. Thus, a layer stack having a planarized layer and two thin-film metal layers separated by a thin dielectric layer have been formed on a surface of a laminated printed wiring board. Portions of the first thin-film metal layer serve as a reference plane to signal lines patterned in the second thin-film metal layer. Furthermore, in one embodiment, the reference plane portions shield, at least partially, the signal lines from electrical fields in the metal layer of the laminated printed wiring substrate.